Analog to digital converters (ADCs) are used for proper operation of conventional wireless communications, enabling digital processing of analog input signals. A principle building block of an ADC is a comparator. FIG. 1 is a simplified block diagram of a basic implementation of a conventional comparator 100, which includes of two inputs 110 and 120, an output 130, and a clock 140. The input 110 receives an input signal (e.g., a radio frequency (RF) signal), and the input 120 receives a reference signal to be compared to the input signal. The output 130 takes one of two possible Boolean logic values of the inputs 110 and 120, discussed below. The clock 140 with a chosen edge (e.g., the rising edge) defines the time instant the comparator 100 is sensitive to the comparison inputs 110 and 120, and is expected to make a decision. The output 130 can be one of two stable states: (i) logic TRUE (or 1) when the input signal at the input 110 is greater than the applied reference at the input 120, or (ii) logic FALSE (or 0) when the input signal at the input 110 is less than the applied reference at the input 120. The output of an ideal comparator is not defined when the input is exactly equal to the reference. However, as a practical matter, the comparator 100 does not take on one of the two allowed logic states, logic 0 or logic 1, for such an input condition, but rather will remain in an indeterminate state, called a metastable state, until additional stimulus, like a noise event, causes an imbalance which pushes the comparator 100 out of the metastable state toward one of logic 0 or logic 1.
Practical regenerative comparators are typically implemented using active circuit elements, such as transistors, in positive feedback configuration. FIG. 2 is a simplified circuit diagram of a conventional regenerative comparator 200 having multiple active circuit elements. The comparator 200 includes cross-coupled transistors 211, 212, 213 and 214, and cross-coupled nodes n1 and n2, which develop an initial starting voltage, called the “seed voltage,” that depends on the input voltage at input 210, and the reference voltage at input 220. The comparator 200 further includes output 230 and clock 240.
FIG. 3 is a graph showing curve 312 indicating the transfer function of the latch from nodes n1 to n2, and curve 321 indicating the transfer function of the latch from nodes n2 to n1. The three points at which the two curves 312 and 321 of the respective transfer functions intersect are the solutions of the circuit, i.e., the possible states. There are two stable states, logic 1 and logic 0, and one metastable state (respectively marked by circles). The rising edge of the clock 240 triggers the comparator 200 and the cross-coupled nodes n1 and n2 settle towards one of the two stable states following a regenerative exponential trajectory until the final logic states are achieved.
The rate at which the comparator 200 regenerates, called the “regeneration time constant,” depends on the process technology used and the architecture of the comparator 200, for example. The comparator output 230 reaches final logic thresholds sooner for large input seed voltages than for small input seed voltages. That is, for small input seed voltages, the comparator output 230 takes longer to regenerate. When an input seed voltage is zero (metastable state), the comparator 200 theoretically stays at the metastable point until an additional event, such as thermal noise imbalance, is enough to push the output 230 to one of the valid logic states, logic 1 or logic 0.
The illustrative comparator 200 can additionally be characterized by the delay from the clock edge until the time the outputs are large enough (usually the noise margin of the logic family). FIG. 4 is a graph showing curve 405 indicating time required to reach a valid logic state versus the difference between the input and the reference voltages. An ADC operates on the inputs that can be different once every clock event. The comparator 200, therefore, has at the most a clock period or a portion of a clock period to make a valid logic decision. When the comparator 200 in an ADC is in a metastable state, a valid logic decision cannot be inferred within the available time, causing an error condition. Arrow 412 indicates the set of voltages that resolve to valid logic levels within available regeneration time. Arrow 411 indicates the set of voltages that do not resolve to valid logic levels within the available time. These are inputs that may cause metastable errors. Arrow 413 indicates the available regeneration time.
An input that causes the comparator 200 in an ADC to be metastable results in a digital output that does not match corresponding portion(s) of the analog input signal, resulting in error. When this error is treated as a noise event, it is observed that such metastable events appear as very large noise-like events that would be highly improbable with the Gaussian statistical models that are usually associated with electronic circuit noise. FIG. 5 is a graph showing curves indicating probability of error versus magnitude of error around desired output. In particular, curve 505 indicates circuit noise predicted by Gaussian statistics, and curve 515 indicates noise due to metastable errors. The dashed portion 515′ of curve 515 beneath curve 505 indicates metastable errors that are indistinguishable from the circuit noise predicted by Gaussian statistics.
In addition to the signal-to-noise ratio (SNR) and/or noise spectral density (NSD), it is increasingly common for ADCs also to be characterized with a metastable error rate. The metastable error rate may be defined as the probability of the ADC generating a noise event larger than expected from a Gaussian statistical model, and is indicated by the shaded area 517, beneath the curve 515 extending beyond the curve 505 in FIG. 5. The shaded area 517 depicts the noise due to metastable errors or other long-tail noise event. The relative importance of the metastable error rate metric depends on the system under consideration. As an example, in many digital communication systems, a metastable error can cause a symbol detection error, but this may be mitigated by recovering the intended message through error correction coding techniques that are usually part of such systems. In a worst case scenario, the receiver comprising the ADC may request a retransmission if the received message cannot be recovered. ADCs used in such systems typically can have poor metastable error rates, often many times in an hour. On the other hand, an ADC used in instrumentation, or aerospace and defense applications, may be used to monitor improbable or infrequent events, and it often may not be possible to repeat the experiment or observation or communication. Such ADCs are designed for lower metastable error rates, such as once per month or once per year, for example.
For example, a metastable error in an ADC used in an oscilloscope with digital triggering may cause the instrument to trigger incorrectly. That is, a metastable error may create a large error exceeding a predetermined trigger level in the oscilloscope even though the actual signal being digitized and monitored by the oscilloscope has not exceeded the predetermined trigger level, resulting in a premature or otherwise incorrect trigger. Another example is a digitizer measuring data from an experiment over a very long duration in “peak hold” mode or “single shot” mode. A metastable error might destroy the outcome of the experiment.
Accordingly, there is a need for a system and method that keeps the metastable error rate sufficiently low, particularly in mission critical systems. This may be achieved through a combination of the metastable error rate specification of the ADC being used, and other system level implementations such as using redundant hardware, examples of which are described by Keane, U.S. Pat. No. 8,736,479 (issued May 27, 2014), which is hereby incorporated by reference.